Your first PCB revision was a learning exercise. That is fine — it is supposed to be. But revision 2 is where you need to start closing gaps systematically, not just fixing the same problems you found on rev 1.
Three patterns account for roughly 80% of avoidable revision 2 failures: not running a DFM review before ordering, underestimating power budget in layout, and failing to document what changed and why.
Run a DFM review before you place the Gerber order
Design for Manufacture (DFM) review identifies issues that will cause problems in assembly — before you spend money on boards and components. Even a 30-minute automated check catches the majority of show-stoppers.
Common DFM issues on revision 2: - Minimum trace/space violations for your chosen fab tier - Paste aperture sizes incompatible with your stencil - Courtyard overlaps that create assembly conflicts - NPTH holes placed in copper zones
Run Gerbers through your fab's DFM checker before ordering. If your fab does not offer one, use JLCPCB or PCBWay's upload tool — both flag common issues.
Model your power budget before routing
Power budget analysis is not glamorous, but skipping it is the single most common cause of hardware failures in battery-powered products.
Build a power budget spreadsheet before you route: 1. List every component and its supply current at nominal and peak 2. Calculate worst-case total draw 3. Verify your regulator can source that current with appropriate derating 4. Model your battery capacity against average current draw to estimate runtime 5. Check your trace widths can carry peak current without significant voltage drop
A 100 mA trace current through 1 oz copper, 0.5 mm wide, 50 mm long loses about 0.15V. On a 3.3V rail, that is a 4.5% drop. Not fatal — but compounding across multiple power stages, it adds up fast.
Document every change with a reason
Revision control without reasoning is nearly useless. When you return to the design 6 months later — or hand it to another engineer — you need to know not just what changed, but why.
Minimum revision log entry: - Date and rev number - Component or area affected - What changed - Why (root cause that drove the change) - Who made the change
This discipline pays off dramatically when you're debugging a field issue, onboarding a new engineer, or preparing a pre-submission technical file.
Test your assembly before potting or enclosing
Leave access for test points on rev 2. You will regret it if you do not. A minimal set of test points for any embedded design: - UART TX/RX for debug output - I2C or SPI bus access on key peripherals - Power rail test points for measurement - Reset and bootloader entry signals
Label them clearly on the silkscreen. It takes 20 minutes in layout and saves hours in debug.